1. Technical Field
This invention is related to the manufacture of memory devices. More importantly, it is directed to a novel method of manufacturing a non-volatile memory device.
2. Background
Non-volatile memory devices are extensively used for storing information. Unlike volatile memory, non-volatile memory is able to retain stored information in the absence of a constant power source. Examples of such devices include Read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically erasable programmable ROM (EEPROM), and flash EEPROM, what is typically referred to as flash memory.
Memory devices are generally composed of arrays of memory cells. A flash memory cell offers the advantage that it may be erased in blocks of data instead of one byte at a time. Each memory cell includes a MOS structure having a gate, a drain, a source and a channel defined between the drain and the source. The gate corresponds to a word line, and the drain or source corresponds to a bit-line of the memory array. A conventional flash memory cell generally includes a layer provided between the gate and the channel for trapping charge carriers. The charge-trapping layer can be a dielectric such as silicon nitride. The memory cell may be programmed by appropriately biasing the gate, the source, and the drain such that charge carriers (electrons or holes) are forced to tunnel or be injected into the trapping layer, effectively trapping the carriers. Applying different biases to the gate, the drain, and the source will allow the memory cell to be read or erased.
As the need for storing more information increases, it becomes necessary to manufacture more memory cells per device, while attempting to either keep the device the same size, or to make it even smaller, requiring increased scalability of memory cells. As the gate size is reduced, the channel between the source and drain region becomes increasingly reduced such that a gradual shorting together of the diffusions of the source and drain may occur. This is known as the “short channel effect”, and it is limited by the total amount of thermal energy transferred to the wafer during the given elevated temperature and duration of the manufacturing process, known as the thermal budget. In order to prevent the short channel effect, it is desirable to reduce the thermal budget. Prior art methods of manufacturing non-volatile memory devices have been limited in their attempts to scale the size of memory cells because of this short channel effect.
FIG. 1 shows a conventional non-volatile read-only memory (NROM) cell 100 representative of an array of memory cells. A dielectric stack consisting of an oxide layer 108, a silicon nitride layer 110, and a second oxide layer 112 is first formed on a p-type semiconductor substrate 102. The silicon nitride layer 110 acts as the charge trapping layer, and the insulating oxide layers prevent the charge from escaping the trapping layer in the absence of the appropriate biases. N-type diffusion regions 104, 106 are formed in semiconductor substrate 102 using conventional implantation methods. Memory device 100 is an n-type MOS transistor with diffusion regions 104, 106 respectively acting as the source and drain thereof. A main gate 114 is formed on second oxide layer 112 and is part of a word-line. By applying appropriate biasing voltages to the main gate 114, source 104, and drain 106, electrons may tunnel into and out of silicon nitride layer 112, as a result of which memory cell 100 may be programmed, read or erased.
The conventional manufacturing method suffers from high word-line resistance. Furthermore, the conventional manufacturing method is less scalable, because the thermal budget associated with the manufacturing process creates short channel effects as the size of the memory cell is reduced.